Education

• Ph.D in Applied Sciences, Delft University of Technology, 2023
• M.S. in Electrical Engineering (cum laude), Delft University of Technology, 2017
• B.S. in Microelectronics (cum laude), Jilin University, 2015

Work experience

• 2024/01-2024/11: Scientific and senior Scientific employee/Postdoc
  • ETH Zurich, Zurich
• 2022/05-2024/01: Senior analog/mixed-signal circuit designer
  • SiTime, the Netherlands
• 2016/08-2017/10: Master thesis intern
  • IMEC Holst Center, the Netherlands

Awards

• IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award, 2021–2022

• Chinese Government Award for Outstanding Self-Financed Students Abroad, 2022

• Co-recipient of the Best Student Paper Award at IEEE IMS (second place), 2023

Co-supervised master students

• 2020-2021: Praneetha Sannidhanam, M.Sc. in EEMCS, TU Delft
  • Thesis Topic: Low-power RF-divider-less wide-band frequency-tracking loop
• 2020-2021: Lennart de Jong, M.Sc. in EEMCS, TU Delft
  • Thesis Topic: High-jitter-tolerance cryogenic clock and data recovery system

Publications

1, Can Livanelioglu^, Long He^, Jiang Gong^, Sina Arjmandpour, Gabriele Atzeni, Taekwang Jang, “A 4.6 GHz 63.3 fsrms PLL-XO Co-Design Using a Self-Aligned Pulse Injection Driver Achieving -255.2 dB FoMJ Including the XO Power and Noise,” accepted to IEEE International Solid-State Circuits Conference (ISSCC), 2025, to appear (^Equally contributed authors).

2, Jiang Gong, Bishnu Patra, Luc Enthoven, Job van Staveren, Fabio Sebastiano and Masoud Babaie, “A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FOMA in 22nm FinFET, ” International Solid-State Circuits Conference (ISSCC) Feb. 2022.

3, Jiang Gong, Yue Chen, Fabio Sebastiano, Edoardo Charbon, Masoud Babaie, “A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications,” International Solid-State Circuits Conference (ISSCC), Feb. 2020.

4, Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie, “A Cryo CMOS PLL for Quantum Applications,” IEEE Journal of Solid-State Circuits (JSSC), 2022.

5, Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie, “A Low Jitter and Low Spur Charge-Sampling PLL,” IEEE Journal of Solid-State Circuits (JSSC), 2022.

6, Jiang Gong, Fabio Sebastiano, Edoardo Charbon, Masoud Babaie, “A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter, 258.9 dB FOM and 65 dBc Reference Spur,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Aug. 2020.

7, Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie, “A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications,” IEEE Custom Integrated Circuits Conference (CICC), April 2021.

8, Jiang Gong, Yue Chen, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie, “A Cryo CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications, ” IEEE Transactions on Circuits and Systems I (TCASI), 2022.

9, Jiang Gong, Yuming He, Ao Ba, Yao Hong Liu, Johan Dijkhuis, Stefano Traferro, Christian Bachmann, Kathleen Philips and Masoud Babaie, “A 1.33mW, 1.6psrms Integrated Jitter, 1.8-2.7 GHz Ring-Oscillator-Based Fractional-N Injection-Locked DPLL for Internet of Things Applications,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Jun. 2018.

10, Yue Chen, Jiang Gong, Robert Bogdan Staszewski, Masoud Babaie, “A Fractional-N Digitally Intensive PLL Achieving 428 fs Jitter and < 54 dBc Spurs Under 50 mV PP Supply Ripple, ” IEEE Journal of Solid-State Circuits (JSSC), 2022.

11, Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza Alavi, Masoud Babaie, “A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving 249.4dB FoM and 59dBc Fractional Spurs, ” International Solid-State Circuits Conference (ISSCC), Feb. 2022.

12, Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken
Yamamoto, Robert Bogdan Staszewski, Morteza Alavi, Masoud Babaie, “A Low Spur Fractional N PLL Based on a Time Mode Arithmetic Unit, Unit,” IEEE Journal of Solid-State Circuits (JSSC), 2022.

13, Luc Enthoven, Job van Staveren, Jiang Gong, Masoud Babaie, Fabio Sebastiano, “A 3V 15b 157uW Cryo CMOS DAC for Multiplexed Spin Qubit Biasing, Biasing,” IEEE Symposium on VLSI Technology and Circuits (VLSI), 2022.

14, L de Jong, JI Bas, Jiang Gong, F Sebastiano, M Babaie, “A 10 Gb/s 275 fsec Jitter Cryo CMOS Charge-Sampling CDR for Quantum Computing Application,” IMS, 2023.

15, M. Mehrpoo, B. Patra, J. Gong, J.P.G. van Dijk, H. Homulle, G. Kiene, A. Vladimirescu, F. Sebastiano, E. Charbon, M. Babaie, “Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers,” IEEE International Symposium on Circuits and Systems (ISCAS) ISCAS), May. 2019.