Welcome to my research group at the University of Electronic Science and Technology of China (UESTC), Shenzhen Institute for Advanced Study.

I received a B.S. degree from Jilin University, Changchun, China, in 2015, and the M.S. and Ph.D. degrees from the Delft University of Technology, Delft, the Netherlands, in 2017 and 2023, respectively. From May 2022 to January 2024, I was a senior analog/mixed-signal circuit designer at SiTime, the Netherlands, focusing on phase-locked loop design for precision timing applications. From January 2024 to November 2024, I was a Post-Doctoral Researcher at ETH Zurich, Zurich, Switzerland. I was a recipient of the IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award for 2021–2022 and the Chinese Government Award for Outstanding Self-Financed (non-government sponsored) Students Abroad, and a co-recipient of the Best Student Paper Award at IMS-2023 (second place).

Research Interests

My research focuses on the analysis and design of the high-performance clock generation system (with an output frequency ranging from kHz to sub-THz) and its building blocks, specifically:

• Clock generator architecture design
• Low-jitter PLL design
• Ultra-low phase noise and wide-tuning-range VCO design
• Low-noise reference oscillator design based on novel BAW/SAW/MEMS resonators
• Ultra-low-noise temperature sensor design
• Novel frequency inaccuracy compensation techniques

I am always looking for self-motivated undergraduate and graduate students with a background in microelectronics to join my group. Each student is encouraged to lead at least one chip design in the advanced CMOS process.

News

• 2024/11: I am looking for Post-Doctoral Researchers, assistant professors, and associate professors to join the group. The detailed information can be found on this website: https://sias.uestc.edu.cn/info/1226/4970.htm (written in Chinese).